1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same and, more particularly, to an MOSFET (metal oxide semiconductor field effect transistor) and a method for fabricating the same in which charge trap is prevented at sidewall spacer of a gate insulating film.
2. Discussion of the Related Art
It is constructed in a general MOS (metal oxide semiconductor) device that a oxide (SiO.sub.2) film is formed on the surface of semiconductor (silicon) and metal is formed thereon. In an FET (field effect transistor), a gate insulating film made of oxide and a gate electrode are successively formed on a silicon substrate of first conductivity type, and source and drain regions are formed beneath the surface of the silicon substrate.
An MOSFET serves to control current (channel current) flowing between source and drain by potential of a gate electrode.
A background MOSFET will be described with reference to the accompanying drawings.
FIG. 1 is a plan view of a background MOSFET, FIG. 2 is a cross-sectional view showing a structure of the MOSFET taken along line I-I' of FIG. 1, FIG. 3 is a cross-sectional view showing a structure of a the MOSFET taken along line II-II', and FIGS. 4A to 4D are cross-sectional views showing process steps of a method for fabricating the MOSFET taken along line I-I'.
In an n channel MOSFET, a field oxide film 2 is formed on a p type semiconductor substrate 1 of a field region. A gate insulating film 3, a gate electrode 5, and a cap gate insulating film 5 are formed on the substrate 1 of an active region. A sidewall spacer 7 is formed on sides of the gate insulating film 3, the gate electrode 4, and the cap gate insulating film. n type lightly doped impurity regions 6 are formed beneath the surface of the semiconductor substrate 1 beneath the sidewall spacer 7. n type heavily doped impurity regions 8, which are used as source and drain regions, are formed at side of the sidewall spacer 7.
A method for fabricating a background n channel MOSFET having the aforementioned structure will be described with reference to the accompanying drawings.
Referring initially to FIG. 4A, a field oxide film 2 is formed on a p type semiconductor substrate 1 of a field region. A gate insulating film 3, made of an oxide film, is formed on the substrate 1 of an active region.
Referring to FIG. 4B, a gate electrode 4 and a cap gate insulating film 5 are formed on a predetermined area of the gate insulating film 3. With the gate electrode 4 and the cap gate insulating film 5 serving as masks, n type impurity ions are lightly implanted.
Referring to FIG. 4C, an insulating film is deposited on the entire surface and then anisotropically etched, thus forming an insulating sidewall spacer 7 on the sides of the gate electrode 4 and the cap gate insulating film 5.
Referring to FIG. 4D, n type impurity ions are heavily implanted with the cap gate insulating film 5 and the insulating sidewall spacer 7 serving as masks, so that n type impurity regions 8, which are source/drain regions, are formed beneath the surface of the semiconductor substrate 1 at the side of the insulating sidewall spacer 7.
The operations of such a background MOSFET will be described below.
A background MOSFET is an LDD MOSFET in which a gate insulating film 3 is formed between a semiconductor substrate 1 and a gate electrode 4 and an insulating sidewall spacer 7 and source/drain regions include lightly doped impurity regions 6 and heavily doped impurity regions 8. Thus, if a voltage of bigger than a threshold voltage is applied to the gate electrode 4, a channel is formed at the semiconductor substrate under the gate electrode 4 so that current flows between source and drain.
In this LDD MOSFET, drain electric field at edge of the gate electrode can be decreased by the resistance of lightly doped impurity regions in comparison with an SD (single drain) structure. Thus, the device performance declined due to hot carrier can be improved.
The background MOSFET has the following problems. Since an oxide film is formed between a substrate and an insulating sidewall spacer, charge trap is generated at the interface of the insulating sidewall spacer and the oxide film and in the oxide film so that the device performance becomes deteriorated.